Power conservation with a synchronous master-slave serial data bus

ABSTRACT

A system is described in which the Master can stop its clock and go into a low-power state (for power conservation reasons) at arbitrary times. Before going into the stopped-clock or low-power mode, the Master checks that the serial bus is idle (defined as both Clock and Data lines being “High”). A latch circuit is provided which is active when them aster is in low-power mode. The latch circuit watches for the very first negative-going clock pulse (from the slave), and its configuration is such that when latched, it holds the clock line low. Holding the clock line low prompts the slave to discontinue efforts to send the data. Stated differently, the slave will not conclude that it had successfully sent its data, and this prompts the slave to retain a copy of its data for later resending.

This application claims the benefit of provisional application60/121,913 filed Feb. 26, 1999.

The invention relates generally to serial bus communication between twodevices, and relates more particularly to synchronous communicationestablished so as to permit effective power conservation in the system.

BACKGROUND

In recent years much attention has been paid to power conservation inpersonal electronic devices including personal computers. Among thedesign goals is the provision of the greatest possible battery life.Efforts to make computers smaller have led to pressure to make thebattery smaller, which leads to a battery of lesser capacity and thusworks against the provision of longer battery life. There is also anupward pressure on the speed of the processor, and as a general matterfaster processors consume more power. It is thus a daunting task toprovide satisfactory battery life, and every possible area of powersavings has to be investigated and considered. Wherever any two systemcomponents connect, for example at two ends of a cable or communicationschannel, it is desirable to design each of the two components so thatthe manner of their interaction favors the efforts to reduce powerconsumption (and thus the efforts to maximize battery life).

In the area of user input devices such as keyboards and pointingdevices, however, the designer of a computer system does not have theluxury of designing the components at both ends of the cable, for thesimple reason that the keyboard or mouse is of a fixed design,conforming to a fixed interface specification. The computer system maybe purchased by the consumer in one store and the external keyboard ormouse in another store.

Those skilled in the art, faced with the goal of conserving power, findthat many measures can contribute to that goal, among them the measureof putting electronics “to sleep” when they are not needed.Alternatively, a productive measure is to cause an item of electronicsto run at a slow clock rate most of the time and to run the item at itsfull clock rate only when absolutely necessary. For example, in the caseof circuitry that responds to user inputs at a keyboard, it may bedesired to allow the circuitry to go to sleep between keystrokes, or toallow it to reduce its clock speed drastically between keystrokes.Similarly in the case of circuitry that responds to user inputs at amouse or other pointing device, it may be desirable to allow thecircuitry to go to sleep or to run slowly between pointing deviceinputs.

As discussed above, in the case where the system designer is able todesign the keyboard or pointing device, any number of techniques may beused to permit such power conservation. One such technique is describedin U.S. Pat. No. 5,585,792, assigned to the same assignee as theassignee of the present invention. But in cases where nothing is knownabout the user input device other than that it conforms to a historicalstandard such as the PS/2 standard discussed herein, then powerconservation is much more difficult. For example, if a system (or partof a system such as a user input device interface) goes “to sleep” orslows its clock rate substantially, the question arises what will happenwhen a user presses a key or moves a pointing device. With mostcommercially available keyboards and pointing devices, what happens isthat a scancode is generated by the user input device. The scancode iscommunicated via a synchronous serial data line to the user input deviceinterface, and the expectation is that the interface will receive thescancode and pass it along to the operating system via a BIOS (basicinput/output system). The difficulty arises that it takes some non-zerointerval of time for the system to “wake up”. During this interval, theentirety of the scancode will have come and gone. The practical effortof this is that the keystroke or pointing device movement is lost. Fromthe user's point of view, this tradeoff is quite unacceptable—even ifpower is to be saved, the user will not tolerate lost keystrokes.

In some system, the effort to conserve power leads to a system in whichthe interface for the user input devices (e.g. a keyboard controller orpointing device controller) will quite literally go to sleep between allkeystrokes. It awakens long enough to process one scancode, and thengoes back to sleep until the next scancode. But in such a system, if thetime required for awakening of the controller were to lead to the lossof a scancode, the practical result would be that all scancodes arelost. This is quite unworkable.

There is thus a great need for an approach according to which a personalelectronic system such as a person computer, or a user input interfacefor such a system, may transition to a low-power mode between userinputs, and may transition to a full-power mode to handle user inputs,without loss of user input information, and to accomplish these resultseven with the use of user input devices about which nothing is knownother than their compliance with historical interface specifications.

SUMMARY OF THE INVENTION

A system is described in which the Master can stop its clock and go intoa low-power state (for power conservation reasons) at arbitrary times.Before going into the stopped-clock or low-power mode, the Master checksthat the serial bus is idle (defined as both Clock and Data lines being“High”). A latch circuit is provided which is active when the master isin low-power mode. A latch circuit watches for the very firstnegative-going clock pulse (from the slave), and its configuration issuch that when latched, it holds the clock line low. Holding the clockline low prompts the slave to discontinue efforts to send the data.Stated differently, the slave will not conclude that it had successfullysent its data, and this prompts the slave to retain a copy of its datafor later resending.

DESCRIPTION OF THE DRAWINGS

The invention will be described with respect to a drawing in severalfigures, of which:

FIG. 1 is a schematic diagram of a synchronous bus system;

FIG. 2 is a schematic diagram of a synchronous bus system including alatch circuit according to the invention; and

FIG. 3 is a block diagram showing a circuit conditioning three portsaccording to the invention.

Where possible, like reference numerals have been given to like elementsin the figures.

DETAILED DESCRIPTION

To describe the invention in detail, it is helpful first to characterizea typical prior-art system in which a user input device such as akeyboard communicates with the system. Turning to FIG. 1, what is shownis what is historically called a “PS/2” bus system. In this system, thebus 50 is a synchronous serial bus and there are only two devices on thebus. The devices are defined respectively as Master 52 and Slave 51, andthe bus 50 connects the devices. The bus 50 is a three-wire bus, definedby a Clock line 70, a Data line 71, and a signal ground line which isomitted for clarity but is understood to provide a signal groundreference between the two devices. (Those skilled in the art appreciatethat most keyboards and pointing devices are electrically connected onlyto the computer and not to anything else, so there need not be a concernfor ground loops. Sometimes the PS/2 bus also provides power forexternal devices.)

Historically the user input device such as a keyboard or pointing deviceis termed the “Slave” and the computer is termed the “Master”. Theinterface circuitry within the computer performing the role of theMaster is historically an 8042 microcontroller integrated circuit or“chip” dedicated to the interface task, omitted for clarity in FIG. 1.The counterpart circuitry within the keyboard is also historically an8051 or other similar microcontroller, also omitted for clarity in FIG.1. Suitable software is loaded into these historical microcontrollerchips so that the keyboard chip may perform scanning of the keyboardmatrix and transmission of the corresponding scancodes over the bus 50,and the interface chip may receive the scancodes and provide thescancode information to the operating system. In historical systems,there is no premium placed on space, weight, parts count or powerconsumption, which permits the use of discrete 8042 chips, but it willbe appreciated by those skilled in the art that it is commonplace tocombine the function of the historical 8042 chip with other functions tosave space, weight, parts count, and power consumption.

As just mentioned, the bus 50 connects two (and only two) devices—aMaster 52 (a.k.a. Host Controller, a.k.a. 8042) and a Slave 51 (Keyboardor Mouse). The single clock line 70 is driven at each end by anopen-collector/open-drain type of semiconductor driver 62, 56, and thesame is true of the single data line driven by drivers 63, 57. (Whilethe drivers are shown as bipolar transistors, other switches such asFETs could be employed.) A pullup resistor 53 is provided so that theidle state of each line is “high”. (The pullup resistor 53 is shown aspart of the Master device 52 but could, in other systems, be provided inthe slave device 51.) Stated differently, each of the devices (master 52and slave 53) is able to drive either of these lines 70, 71 “low” at anytime. Also connected to respective ends of the bus lines 70, 17 are linereceivers 64, 65, 54, 55 which are preferably Schmitt triggers for noiseimmunity.

The protocol between the master and slave defines that all clock signalsfor the data transfers are generated by the slave. As the communicationsare intended to be bidirectional, the protocol further defines that datasignals can be generated by either the master or the slave. The protocolalso defines that any transfer of data, regardless of direction, isinitiated by pulling the data line low.

It will thus be appreciated that the slave device 51 transmits via lines59 and 61, using line 59 to clock data on line 61. Similarly the masterdevice 52 transmits via line 69, responding to clock signals received online 66 to clock data on line 69. Reception at the slave device 51 isvia lines 58 and 60, with line 58 clocking data for line 60. Receptionat the master device 52 is via lines 66 and 68, with line 66 clockingdata for line 68.

In the case of a transfer of data from Slave to Master, after the Slavepulls the data line low, it commences the generation of negative-goingclock pulses. In this way the bits of data are clocked across the dataline.

In the case of a transfer of data from Master to Slave, after the Masterpulls the data line low, it waits until such time as the Slave commencesthe generation of negative-going clock pulses. The bits of data areclocked across the data line by the Master in response to the pulses onthe clock line that are generated by the Slave.

It is necessary, of course, to consider the case of a collision whenboth the Master and Slave want to send data at the same time. Theprotocol defines that in this case, “Master sends to Slave” mode haspriority. This condition is recognized by the Slave at a time when itwants to send data, but finds the Data line already “Low”. The Slave isrequired, under the protocol, to refrain from sending data until theMaster-to-Slave transfer has completed and the bus has returned to anidle or quiescent state.

A final aspect of the protocol is particularly significant. At any timebefore a Byte data transfer, or at any time up to the last data bitduring the transfer—the Master 52 may invoke an aspect of the protocoldesigned to abort the data transfer, and does so by holding the Clockline 70 “Low” (minimally, it is required to hold the Clock “Low” atleast for the duration of the longest possible Clock cycle—defined as˜100 uS, but there is no Maximum limitation on how long the Clock can beheld “Low”). It does so via clock control line 67. The Slave device isrequired, under the protocol, to monitor the clock line 70 during a timewhen the Slave was not itself holding the clock line low. In this event,the Slave makes note that its data transmission did not succeed. TheSlave is required to re-send the data Byte as soon as the Bus becomes“free” (e.g. the Clock line 70 is returned to the Idle “High” state), orat any convenient time thereafter.

Among the possible exchanges of data between Master and Slave is anexchange in which the Master sends a command to the Slave, and in whichthe Slave is obligated to provide a response. The protocol defines thatthe response must be made promptly. In the event that the Masterinhibits data flow as described above by holding the clock line 70 low,the protocol implies that the Slave should attempt to resend the data assoon as the bus becomes available. In the case that the Master pulls theclock line low at any time after the first clock pulse has been assertedand up to the tenth pulse of the message byte, the Slave will have tore-transmit the byte when the bus becomes available (that is, when theclock line is released to go high again). The Master will typicallyelect to abort a transmission using this method if it becomes busy andis unable to process the incoming byte, or if it needs to override thedata transmission from the slave in order to issue a command. In thelatter case, depending on the type of command issued the slave may ormay not need to re-transmit the aborted byte (if for example the commandis a “reset” command the Slave has to clear its output buff andreinitialize itself). It is also important to note that according to theprotocol, if the Master applies this method at the eleventh clock pulse,corresponding to the last bit of the transmitted byte, the slave ispermitted to assume that the message byte has been received intact andwill not attempt to transmit it.

In the system according to the invention, advantageously the Master 52can stop its (internal) clock and go into a low-power state (for powerconservation reasons) at arbitrary times, as will now be described.Before going into the stopped-clock or low-power mode, the Master checksthat the serial bus is idle (defined as both Clock and Data lines being“High”). What follows next is one of two events: (1) the Master returnsto normal clock operation (normal power mode); or (2) the Slave attemptsto send data to the Master. In the former case, the Master is able toreceive later data from the Slave just as in the prior art. In aprior-art system, however, the latter event (the slave attempting tosend data at a time when the master has a stopped or very slow clock)would result in loss of data from the slave. In practical terms, akeystroke or pointing device movement could be lost.

Turning now to FIG. 2, advantageously, in the system according to theinvention, a latch circuit 81 is provided which is active when themaster is in low-power mode. The latch circuit watches for the veryfirst negative-going clock pulse (from the slave), and its configurationis such that when latched, it holds the clock line 70 low via line 82.As described above, holding the clock line 70 low prompts the slave 51to discontinue efforts to send the data. Stated differently, the slave51 will not conclude that it had successfully sent its data, and thisprompts the slave 51 to retain a copy of its data for later resending.

The configuration of the latch 81 is such that when it is triggered, itholds the clock line 70 low. At some later time the Master 52 restartsits clock (or returns to full-power mode) and is in a position to beable to receive serial data from the slave. (The return of the Master tonormal clock or normal power mode may be prompted by the latching of theclock as detected at line 66, or may happen for other reasons. In theformer case, the clock line serves as an interrupt which causes a returnto full-power mode.) As soon as the Master 52 is running (which in apreferred embodiment takes only a few milliseconds), the master 52resets the Latch circuit 81 by means of line 80. This releases the Clockline 70 from the “Low” state. At some convenient time the Slave 51 willre-send the last byte data transmission.

Those skilled in the art will appreciate that there is a penaltyassociated with the use of the latch 81 in connection with low-powermode, namely that there may be a delay of a few milliseconds until themaster's internal clock has stabilized and them aster is ready toprocess incoming data in real time. Experience, however, shows that thisdelay does not affect system performance perceptibly. If the delay isacceptable, the desirable result is that even during an interval oflow-power mode, the Slave 51 can start sending data at any time, evenduring times when the Master 52 is unresponsive, and yet not data lossoccurs.

It should be appreciated that in commercial applications it iscommonplace to have a system which responds to two or more user inputdevices. For example there may be built-in keyboard, a connector toreceive an external keyboard, and a connector to receive a mouse orother pointing device. Thus it is desirable to provide a system in whichthe master may transition to a low-power or clock-stopped mode, and yetmay respond to two or more user inputs from two or more slave devices,all without the danger of losing user input information. Turning now toFIG. 3, what is shown is a preferred circuit which will condition threePS/2 ports (at lines 92, 93, and 94) at the same time for the Mastercontroller. There is in principal no limit to the number of PS/2 portsone can incorporate in a single controller, only the circuit should berepeated as many times as necessary. In this embodiment the latch 90 isa 74HCT4053. The master rests the latch by means of control line 91.

Note that the assertion of the clock low signal by the Master may occurat any time during the transmission of the first ten bits of the bytemessage. A second implementation could consist of a counter or othersimilar circuit that is capable of asserting the clock line low after apredetermined number of incoming clock pulses. Another implementationuses the inhibit instead of the abort feature of the protocol and can beimplemented by a ten-bit minimum length shift register and associatedcircuitry that will hold the clock line low after the reception of thetenth bit of the message. In this case the Slave will not have tore-transmit the byte (assumes that the byte has been received). TheMaster can retrieve the information of the received byte from the shiftregister and re-enable the bus as soon as it is ready to receive thenext one. This method reduces bus traffic (re-transmissions at an extrahardware cost (shift register and associated circuitry).

What is claimed is:
 1. A system comprising a master device and slavedevice communicatively coupled by a serial synchronous communicationsline, said communications line defining a clock line and a data line,each of said clock and data lines biased high, each of said master andslave having a respective clock line driver actuable to pull the clockline low, each of said master and slave having a respective data linedriver actuable to pull the data line low; said master device disposedto operate at a first power level and at a second lower power level;said system further comprising a latch comprising a line driver actuableto pull the clock line low, said latch responsive to said master devicebeing at said second power level, and responsive to said clock linetransitioning to a low level, for actuating its line driver therebyholding the clock line low; said latch further responsive to said masterdevice reaching its first power level for deactuating the line driver ofthe latch.
 2. The system of claim 1 wherein the latch and master deviceare further characterized in that the master device is responsive toactuation of the latch for transitioning the master device to the firstpower level.
 3. The system of claim 1 wherein the slave devices haltstransmission of data on the communications line in the event of theclock line being held low other than by the clock line driver of theslave device.
 4. A system comprising a master device communicativelycoupled to a serial synchronous communications line, said communicationsline defining a clock line and data line, each of said clock and datalines biased high, said master having a clock line driver actuable topull the clock line low, said master having a respective data linedriver actuable to pull the data line low; said master device disposedto operate at a first power level and at a second power level; saidsystem further comprising a latch comprising a line driver actuable topull the clock line low, said latch responsive to said master devicebeing at said second power level, and responsive to said clock linetransitioning to a low level, for actuating its line driver therebyholding the clock line low; said latch further responsive to said masterdevice reaching its first power level for deactuating the line driver ofthe latch.
 5. The system of claim 4 wherein the latch and master deviceare further characterized in that the master device is responsive toactuation of the latch for transitioning the master device to the firstpower level.
 6. A method for use in a system comprising a master deviceand slave device communicatively coupled by a serial synchronouscommunications line, said communications line defining a clock line anda data line, each of said clock and data lines biased high, each of saidmaster and slave having a respective clock line driver actuable to pullthe clock line low, each of said master and slave having a respectivedata line driver actuable to pull the data line low; said master devicedisposed to operate at a first power level and at a second lower powerlevel; said system further comprising a latch comprising a line driveractuable to pull the clock line low; the method comprising the steps of:causing the master device to enter said second power level; respondingto said clock line transitioning to a low level by actuating the linedriver of the latch thereby holding the clock line low; responding tosaid master device reaching its first power level by deactuating theline driver of the latch.
 7. The method of claim 6 further comprisingthe step of responding to actuating the latch by causing the masterdevice to transition to the first power level.
 8. The method claim 6further comprising the step of responding to the event of the clock linebeing held low other than by the clock line driver of the slave deviceby halting transmission of data on the communications line by the slavedevice.
 9. The method of claim 6 further comprising the step ofresponding to actuating the latch by causing the master device totransition to the first power level.
 10. A method for use in a systemcomprising a master device communicatively coupled to a serialsynchronous communications line, said communications line defining aclock line and a data line, each of said clock and data lines biasedhigh, said master having a clock line driver actuable to pull the clockline low, said master having a respective data line driver actuable topull the data line low; said master device disposed to operate at afirst power level and at a second lower power level; said system furthercomprising a latch comprising a line driver actuable to pull the clockline low; the method comprising the steps of: causing the master deviceto enter said second power level; responding to said clock linetransitioning to a low level by actuating the line driver of the latchthereby holding the clock line low; responding to said master devicereaching its first power level by deactuating the line driver of thelatch.
 11. A system comprising a master device and first and secondslave devices, each slave device communicatively coupled with the masterdevice by a respective serial synchronous communications line, each saidcommunications line defining a clock line and a data line, each of saidclock and data lines biased high, each of said master and slave having arespective clock line driver actuable to pull the respective clock linelow, each of said master and slave having a respective data line driveractuable to pull the respective data line low; said master devicedisposed to operate at a first power level and at a second lower powerlevel; said system further comprising first and second latchescorresponding to respective slave devices, each said latch comprising aline driver actuable to pull a respective clock line low, each saidlatch responsive to said master device being at said second power level,and responsive to said respective clock line transitioning to a lowlevel, for actuating its line driver thereby holding the respectiveclock line low; each said latch further responsive to said master devicereaching its first power level for deactuating the line driver of thelatch.
 12. The system of claim 11 wherein the latch and master deviceare further characterized in that the master device is responsive toactuation of each of the first and second latches for transitioning themaster device to the first power level.
 13. The system of claim 11wherein each slave device halts transmission of data on its respectivecommunications line in the event of the respective clock line being heldlow other than by the respective clock line driver of the slave device.14. A system comprising a master device communicatively coupled to firstand second serial synchronous communications lines, each saidcommunications line defining a respective clock line and a respectivedata line, each of said clock and data lines biased high, said masterhaving respective clock line drivers actuable to pull the respectiveclock lines low, said master having respective data line driversactuable to pull the respective data lines low; said master devicedisposed to operate at a first power level and at a second lower powerlevel; said system further comprising first and second latchescorresponding to the first and second communications lines, each latchcomprising a respective line driver actuable to pull the respectiveclock line low, each said latch responsive to said master device beingat said second power level, and responsive to said respective clock linetransitioning to a low level, for actuating its respective line driverthereby holding the respective clock line low; each said latch furtherresponsive to said master device reaching its first power level fordeactuating the respective line driver of the latch.
 15. The system ofclaim 14 wherein the latches and master device are further characterizedin that the master device is responsive to actuation of each said latchfor transitioning the master device to the first power level.